Technology scaling trends pose a significant challenge in designing reliable computer systems due to the occurrences of transient faults. A major source of transient faults in computer circuits is due to the generation of soft errors which occur when the energetic neutrons coming from space or the alpha particles arising out of packaging materials hitting the transistors. A soft error may manifest itself as a bit flip in a memory element or it can occur in any internal node of a combinational logic and subsequently propagate to and be captured in a latch. In the past, soft errors have been handled at the circuit level using schmitt triggers, adding duplicate cells and clamping the voltage between the duplicate nodes, and addition of pass transistors to filter the random glitches that lead to soft errors. However, these approaches for avoiding soft errors in logic circuits often incur significant overheads in terms of delay, area and power. Although, soft errors have been a greater concern for memory elements, technology trends like smaller feature sizes, lower voltage levels, higher operating frequency and reduced logic depth, are projected to increase the soft-error rate (SER) in combinational logic beyond that of unprotected memory elements. In a recent study, the SER of logic circuits were quantified in technology nodes from 600 nm to 50 nm and it was projected that by 2011, the SER in logic circuits will increase by nine orders of magnitude and will essentially be comparable to unprotected memory.
Several approaches have been proposed in the literature to protect VLSI circuits against soft errors. Since memories were particularly susceptible to radiation induced soft errors, many approaches have focused to radiation-harden memory cells and few have actually focused on prevention of soft errors in logic circuits. Many approaches known in the art mitigate soft errors using detection and correction techniques mostly by using spatial and temporal redundancy. In the prior art, time redundancy is exploited to detect and recover from soft-errors. Additionally, a technique for correction of logic soft errors using c-elements has been proposed. It is known to add concurrent error detection circuits to nodes in logic circuits which have high soft error susceptibility. Some works reported in literature prevent the generation of transient faults by sizing the individual gates of a logic circuit. Prior art designs asymmetric logical masking probability of nodes in a logic circuit is exploited to selectively resize gates. An optimization framework based on geometric programming is used for simultaneous dual-VDD assignment and sizing in also known in the art. The authors of the present invention have proposed a technique to reduce SER in logic circuits by simultaneous sizing and flip-flop selection. Soft errors can also be prevented in logic circuits by using various circuit level optimization techniques. In the art soft error protection in domino logic and sequential cells is achieved by explicitly adding capacitors to the feedback node. These ideas have been extended to combinational logic circuits. However, as the stored charge in the keeper becomes smaller due to technology scaling, the technique becomes inefficient in fighting transient glitches due to radiation strikes. In other prior art solutions, gates are locally duplicated and the duplicate nodes are connected by a voltage damper circuit. This prevents the output node of the gate and its duplicate node from deviating in voltage due to a radiation strike. This technique, however, doubles the area and power overhead. The effect is especially severe for complex cells or cells with higher drive strengths. Adding shadow gates for such cells with a large silicon footprint makes the area and power overhead significant. In another prior art solution, the logic gates that are bombarded by radiation strikes are isolated using complimentary pass gates. The complimentary pass gates act as a low pass filter and filters out transient voltage pulses due to a radiation strike. In an additional prior art solution, a class of soft error masking circuits is proposed using a Schmitt trigger circuit. These techniques, however, can achieve a marginal reduction in the radiation induced glitch magnitude but cannot completely eliminate the transient.
A need exists in the art for an improved methodology and circuit for the reduction of soft errors in logic circuits that provides a marginal increase in delay, power consumption and area overhead.